1. Field of the Invention
This invention relates to L1-L2 latch chains, and more particularly to an improved programmable delay circuit for the L2 latch clock.
2. Description of Background
As will be appreciated by those skilled in the art, a latch circuit of the type contemplated by this invention has a data and a clock input. The data input state at the leading clock edge is transferred to the latch output. The output state is retained after the trailing edge of the clock, independent of changes in the input data. A common approach to memory logic uses one latch L1 as a master latch and another latch L2 as a slave latch, with the output of L1 coupled to the input of its associated L2 latch. The latches are connected in series to from a chain and separate clock signals (C1 and C2 respectively) are used to clock the L1 latches and the L2 latches. As will also be appreciated by those skilled in the art, one L2 latch is associated as a slave with each L1 latch in order to allow scan testing of the latch chain. In certain L1/L2 latch chains, where there is a large time delta between the data output of L1 and the data arrival at L2, the data is not reliably captured in the L2 latch. The prior art has proposed the use of a delay circuit to delay the clock signal C2 to the L2 latch. However, these proposals have not been all together successful. One problem with prior art proposals for delaying the L2 clock signal it that it introduces glitches. During test scan operations, the set(0-3) signals (FIG. 1) are constantly switching. This can cause glitching (unintended false switching to 1 or 0) on the delay_out signal, which can corrupt the data flow from L1 to L2. This corrupted data flow can directly affect the output since there is no other latch to preserve data integrity after the L2 latch. Another limitation of prior art C2 clock delay circuits is that they alter the duty cycle of original C2 signal.